By Jackson M.A

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The communication-link must therefore also be capable of transferring DC information. As the relative timing between the two switches of the inverter is of fundamental importance to the operation of the inverter, the two drive signals must be received without any time skewing, loss of information, or pulse width distortion relative to the other sides drive signal. When the high-side switch is on, the midpoint will be at the supply potential and the full supply voltage will be applied across the communication-link and hence it must have an isolation voltage rated accordingly.

High frequency layout techniques are imperative and were used through out the whole circuit. The clock signal was generated by a variable frequency oscillator which enabled the switching frequency to be adjusted without affecting the dead-time. The frequency range was from 50 kHz 6 MHz, and the duty cycle range was from 25% to 48% (Duty cycle could not be adjusted this low at the lower frequencies). The maximum time skew between the two drive signals was in the order of 2ns. 5%. 8. 8 Final Circuit used to generate the Drive signals 74ACT08 Chapter4.

The dead-time between switching transitions must be selected by the designer and for this simulation it was chosen to be 10% of the period (20ns). 4. 4 shows the midpoint voltage, V(M1:s), and the load current, I(L1), as indicated by the voltage and current markers on the circuit diagram. The second plot shows the voltage across, (150-V(M1:s)), and the current through, ID(M1), the high side MOSFET. It should be noted that the current, ID(M1), is the total switch current as it includes the current into the output capacitance which is an integral part of the MOSFET.

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