By Mladen Berekovic, Christian Müller-Schloer, Christian Hochberger, Stephan Wong

This booklet constitutes the refereed complaints of the twenty second overseas convention on structure of Computing structures, ARCS 2009, held in Delft, The Netherlands, in March 2009.
The 21 revised complete papers offered including three keynote papers have been rigorously reviewed and chosen from fifty seven submissions. This year's unique concentration is determined on power knowledge. The papers are prepared in topical sections on compilation applied sciences, reconfigurable and functions, titanic parallel architectures, natural computing, reminiscence architectures, enery wisdom, Java processing, and chip-level multiprocessing.

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Afterwards, the space-time mapped program is synthesized. The hardware synthesis step generates a completely platform and language independent register transfer level (RTL) description of the hardware. , FPGA type), finally converted into HDL code of choice. 4 Problem Statement The synthesis of loop programs on hardware has been a deeply studied problem. , tiling and clustering). Fig. 2(a) shows the iteration space without data dependencies of a 4-tap FIR filter which is used to illustrate the fundamental difference between the two approaches.

IF (j==0 and k==0) THEN { u[i,j,k] = u_in[i]; y[i,j,k] = a[i,j,k] * u[i,j,k]; } ELSEIF (i==0) THEN u[i,j,k] = 0; IF (j>0) THEN y[i,j,k] = y[i,j-1,k] + a[i,j,k] * u[i,j,k]; ELSEIF (k>0) THEN y[i,j,k] = y[i,j+P-1,k-1] + x[i,j,k]; IF (j==P-1 and k==N/P-1) y_out[i] = y1[i,j,k]; } } } Fig. 5. Partitioned FIR filter 22 F. Hannig, H. Dutta, and J. Teich PE contains one MUL and one ADD unit. The tiles are processed global sequentially. The partitioned FIR filter is shown in Fig. 5. The major questions that need to be answered on basis of several algorithms are: – What is the quantitative trade-off in terms of hardware cost, performance, and power between loop unrolling and partitioning?

However, apart from one outlier, the throughput of the processor array approach is 11 to 42% higher as compared with the unrolled approach. In Fig. 6, the throughput itself, normalized by the gate count, and the throughput per mW is shown. In Fig. 7, the speedup characterizes the performance gain with respect to the throughput for the FIR filter algorithm. The cost increase is related to the gate count of the designs. In the single PE solution of the FIR filter, the 64 iterations are executed sequentially within one PE.

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